We will be part of the Linux Garage, a new section they are adding this year.  Linuxdevices.com had a good write up. Also you can check out the expo site here. We will be there August 5-7. We hope to have several demos up including: a GPS system, servo controller and audio device.

We now have initial production quantities available. If you are interested in a Linuxstamp please email me pthomas8589 _at_ gmail _dot_ com. They are $120 plus shipping. Right now I can just accept paypal. Hopefully we will have a website up soon.

I have the POE working on the Linuxstamp. I’ll go through all of the equipment that I am using. To supply the power I looked at POE injectors, but they didn’t seem that economical for one port so decided on the Trendnet POE switch. It has 4 POE ports and 4 regular ports. Next is the ethernet connector on the Linuxstamp. After much looking I found this Pulse Jack. The only thing I don’t like about it is that it is over an inch long. All the jack is doing is bringing out the centers of the primary transformers (where the 48v is). I then run the 48v to a prototype motherboard where I have the Ag9050. The Ag9050 is an isolated 48v -> 5v POE module. The only other component is a 470uF cap on the 5v output of the Ag9050 (Linuxstamp 5v input). Now the Linuxstamp can run without a wall wart.

Here is a pic of one of the first prototypes. Things are going very well. U-boot is working, and we’re working on getting the rest of the system working.

http://groups.google.com/group/linuxstamp

We are very close to having prototypes of the linuxstamp. I have updated the Linuxstamp page quite a bit, and I will post some pics of the board soon. Stay tuned for more updates.

I thought I would try and play with kernel drivers some. I found this site, and it was very helpful for getting started. I tried this out on a x86_64 box running Fedora 6. I created dirt simple module following the tutorial. I had one c file named “hello.c” with the following contents:

#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>

module_init(hello_init);
module_exit(hello_exit);

The “Makefile” contained one line:

obj-m := hello.o 

I then used the following compile command:

 make -C /usr/src/kernels/2.6.20-1.2962.fc6-i586 M=`pwd` modules

Up to this point everything was working pretty much as the tutorial described. The problem came when I tried to load the module:

/sbin/insmod hello.ko

Resulting in the following error:

insmod: error inserting ‘hello.ko’: -1 Invalid module format

Upon further investigation I found my running kernel and my build kernel wern’t quite the same /proc/version reads  2.6.20-1.2944.fc6 which is different. I don’t know why Fedora didn’t install 2.6.20-1.2944.fc6 when I installed kernel-devel. You can also see this error in using dmesg. So how do you trick insmod to load the module anyway? You can’t, but you can trick modprobe. The problem with modprobe is it needs to know where your module is so you must add a line to /lib/modules/2.6.20-1.2944.fc6/modules.dep

/path_to_module_dir/hello.ko:

Now modprobe will work with the following command:

 /sbin/modprobe hello –force-vermagic

And you can unload it with:

 /sbin/rmmod hello

Now if you run dmesg it should show our entry and exit print statements.

Today I saw a slashdot posting for a tear down of the iPhone. Besides being very interesting in general one thing struck me, and that was the main processor. Not only was this thought to be an ARM11 part, but it seems to have a 256 MB of SDRAM stacked in the same package. This reminds me of a tear down I saw for the Nokia 7280. This is a very similar idea except this time the memory stack is a separate chip from the processor. I have the paper copy of this article, and the picture shows the memory stack chip soldered directly on top of the processor. The memory stack in the 7280 is also from Samsung, but it includes 3 types of memory: NAND flash, NOR flash and SDRAM. Vertically stacking dies has become very important to reducing board area. I especially like the way the stack on the 7200 works because then the package for the processor can stay the same, but incremental advances in the memory stack can be made.

Traditionally processors have been built to only be a processor. In the PC world the processor has been directly connected to only the northbridge (Even this is changing e.g. AMDs integrated memory controller). This created a system where the northbridge and the southbridge would connect the processor to the outside world (ethernet, audio, video, keyboard etc…).

Enter the 8-bit embedded processor.

At the same time that x86 PCs were becoming wildly popular small 8-bit embedded microcontrollers were being used more frequently (such as the PIC). While these devices still have a processor the peripherals to interact with the outside world are built onto the chip (PWM, A/D, D/A, serial communication etc…). Notice that these embedded microcontrollers interact with the outside world in a very different way their PC counterparts.

Mixing of worlds

With the introduction of ARM processors we see several features that existed in the embedded microcontroller world as well as the x86 world. I know ARM9 processors are latter in the development of the ARM line, but I will use them as an example. From the x86 world ARM9 takes 32-bit operation and a MMU (to handle virtual memory). From the microcontroller world ARM9 takes integrated peripherals. ARM takes this one step further, they developed a standard on chip interconnect for peripherals the AHB (advanced highspeed bus) and the APB (advanced peripheral bus). Today we see many chip companies taking an ARM core and integrating it with their own cores, peripheral cores from ARM, and third party cores. This has developed a large ecosystem of ARM based SOCs. The processor/peripheral combination has become known as the SOC (System On Chip).

Other interesting SOCs.

I have talked a lot about ARM SOCs, but there are other SOCs that can run linux and have integrated peripherals. I have run into a few other very interesting SOCs. The first is Sun’s Niagara II processor. This so called server on chip, an 8-core SPARC processor, integrates several interesting peripherals including: dual 10 gigabit ethernet ports, PCI-E x8 and an integrated memory controller. Sun’s T1, the predecessor of Niagara II, was open sourced (Sun has not decided on wether to open source Niagara II). One company, Simply RISC, has taken the T1 stripped off many of the server features, reduced it to one core and added a wishbone interface. Wishbone is another on chip interconnect similar to AHB and APB. Simply RISC has named their processor the S1.

Future

I am interested in two trends here. The first is open source moving beyond software, and the second is creating even tighter integration in the SOC world. For example how about a SOC based on the S1 core that has an 802.11 radio next to it?

The mboard 1 is the first motherboard concept for the linuxstamp. It is still in the planning stages, so if there is a feature you want add it to the wish list.