So easic is now advertising their capability to produce ASICs based on the Leon3 processor. The Leon3 is a 32-bit open source Sparc processor. To my knowledge no one has taken advantage of this to create a general purpose processor available to the public.
So there are now 4 open source Sparc implementations, and not a single part you can buy at digikey. The first implementation is the T1 processor from Sun. The T1 is an 8-core 64-bit chip, and it is an actual part that Sun uses. However, it is not low cost, low power or available through standard distribution. The second implementation is the successor to the T1, the T2. The T2 is an impressive chip, Sun likes to call it a “server on a chip”, and it has many features built in including: dual 10 Gbe, 8x PCI express and memory controllers. The third implementation is the S1 which is a derivative of the T1 created by Simply RISC. The cool feature about the S1 is that it implements a wishbone interface, which is the SOC bus preferred by the folks at opencores.org. And the fourth implementation I mentioned earlier, the Leon3 from Gaisler Research. The nice thing about the Leon3 is that it uses the AHB (same bus that ARM uses), and they have an extensive IP library of peripherals to use with the Leon3.
I am fascinated by the activity we are seeing, buy I’m still waiting for the chips. Are there other people interested in a general purpose Leon3 processor (not an FPGA implementation)?
